研究者総覧 - 大竹　哲史

オオタケ　サトシ
大竹　哲史

所属大分大学理工学部知能情報システムプログラム

職種教授

論文
論文	IC Seating Inspection Using Laser Reflection Imaging and PaDiM IEEE Global Conference on Consumer Electronics 2025/09
論文	IoT-Enabled Sake Brewing Data Management IEEE International Conference on Consumer Electronics - Taiwan 2025/07
論文	Vibration Measurement and Analysis of Rails and Signal Bonds on the Kyushu Shinkansen Proceedings of IEEE International Conference on Consumer Electronics Asia,417-421頁 2024/11
論文	Vibration Measurement Experiment of Rails at Shinkansen Rail Yard in Kumamoto. GCCE,318-320頁 2023/10
論文	A Method of Controlling Devices Remotely in Online Embedded System Engineer Training. ICCE-Taiwan,495-496頁 2023/07
論文	Field Monitoring System for Frost Damage Warning and Quality Difference Analysis of Tea Leaves. ICCE-Taiwan,139-140頁 2023/07
論文	Hardware Implementation of Constant Monitoring System of Fetal Heart Sounds. ICCE-Taiwan,663-664頁 2023/07
論文	A robust method of IC seating inspection in burn-in sockets using Hough transform ICCE-TW,1-2頁 2022/07
論文	Vibration Measurement of Signal Bonds for Shinkansen IEEE International Conference on Consumer Electronics(ICCE),1-5頁 2021/01
論文	A Warning System with Multiple Sensors for Avoiding Collision of Bicycles IEEE International Conference on Consumer Electronics - Taiwan(ICCE-TW),1-2頁 2020/09
論文	Temperature Monitoring in Shinkansen Signal and Communication House 2020 IEEE International Conference on Consumer Electronics (ICCE),1-3頁 2020/01
論文	A Koji Temperature Monitoring System IEEE International Conference on Consumer Electronics - Taiwan(ICCE-TW),1-2頁 2019/07
論文	A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures 28th IEEE Asian Test Symposium(ATS),31-36頁 2019
論文	Factory Environment Monitoring: A Japanese Tea Manufacturer's Case IEEE International Conference on Consumer Electronics(ICCE),1-3頁 2019
論文	Monitoring Sake Brewing Processes with Compact Wireless Sensors 9th IEEE International Conference on Consumer Electronics(ICCE-Berlin),319-323頁 2019
論文	A Mash Temperature Monitoring System for Sake Brewing 2018 IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2018 2018/08/27
論文	A Method of Hardware-Trojan Detection Using Design Verification Techniques Complex, Intelligent, and Software Intensive Systems - Proceedings of the 12th International Conference on Complex, Intelligent, and Software Intensive Systems(CISIS),978-987頁 2018
論文	An approach to LFSR-based X-masking for built-in self-test 18th IEEE Latin American Test Symposium(LATS),1-4頁 2017
論文	A method of LFSR seed generation for hierarchical BIST Proceeding of 2015 10th International Design and Test Symposium, IDT 2015,118-123頁 2016/02/01
論文	A Delay Measurement Mechanism for Asynchronous Circuits of Bundled-Data Model 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems(DDECS),243-248頁 2015
論文	A Method of Diagnostic Test Generation for Transition Faults 21st IEEE Pacific Rim International Symposium on Dependable Computing(PRDC),273-278頁 2015
論文	A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults 16th Latin-American Test Symposium(LATS),1-6頁 2015
論文	10.4 フィールドテストデータの蓄積とその活用(第10章:将来の課題,<特集>ディペンダブルVLSIシステム) 日本信頼性学会誌信頼性 35 (8),513 2013
論文	A Method of LFSR Seed Generation for Scan-Based BIST Using Constrained ATPG Seventh International Conference on Complex, Intelligent, and Software Intensive Systems(CISIS),755-759頁 2013
論文	DART: Dependable VLSI Test Architecture and Its Implementation PROCEEDINGS INTERNATIONAL TEST CONFERENCE 2012 2012
論文	Delay Testing: Improving Test Quality and Avoiding Over-testing IPSJ Transactions on System LSI Design Methodology 4,117-130頁 2011/08/10
論文	F-Scan: A DFT Method for Functional Scan at RTL IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E94D (1),104-113頁 2011/01
論文	F-Scan Test Generation Model for Delay Fault Testing at RTL using Standard Full Scan ATPG 2011 16TH IEEE EUROPEAN TEST SYMPOSIUM (ETS),203-203頁 2011
論文	Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits Proceedings of the 19th IEEE Asian Test Symposium,206-211頁 2010/12
論文	A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification. IEICE Transactions 93-D (7),1857-1865頁 2010/11
論文	A synthesis method to propagate false path information from RTL to gate level 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010,197-200頁 2010/04
論文	Enabling False Path Identification from RTL for Reducing Design and Test Futileness. Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Vietnam, January 13-15, 2010,20-25頁 2010/01
論文	A Method of Unsensitizable Path Identification using High Level Design Information 5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era 2010
論文	Constrained ATPG for Functional RTL Circuits Using F-Scan 2010 IEEE International Test Conference 2010
論文	Delay Fault ATPG for F-Scannable RTL Circuits IEEE Int. Symp. on Communications and Information Technologies 2010
論文	A Circuit Failure Prediction Mechanism (DART) for High Field Reliability Proc. IEEE 8th International Conference on ASIC (ASICON2009),581-584頁 2009
論文	A Synthesis Method to Alleviate Over-testing of Delay Faults Based on RTL Don't Care Path Identification IEEE VTS'09 (27th VLSI Test Symposium),71-76頁 2009
論文	Fast False Path Identification Based on Functional Unsensitizability Using RTL Information 14th Asia and South Pacific Design Automation Conference (ASP-DAC 2009),660-665頁 2009
論文	Unsensitizable Path Identification at RTL Using High-Level Synthesis Information 16th IEEE International Test Synthesis Workshop (ITSW 2009) 2009
論文	Acceleration of test generation for sequential circuits using knowledge obtained from synthesis for testability IEICE Transactions on Information and Systems E90-D (1),296-305頁 2008
論文	Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation IFIP International Federation for Information Processing 249,301-306頁 2008
論文	Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors IEICE Transactions on Information and Systems E91-D (3),763-770頁 2008
論文	Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-Cycle Paths Proc. of IEEE the 17th Asian Test Symposium,125-130頁 2008
論文	Efficient path delay test generation based on stuck-at test generation using checker circuitry IEEE/ACM International Conference on Computer-Aided Design,418-423頁 2007
論文	False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults IEEE 16th Asian Test Symposium,65-68頁 2007
論文	Generation of power-constrained scan tests and its difficulty IDT 2007: SECOND INTERNATIONAL DESIGN AND TEST WORKSHOP, PROCEEDINGS,71-+頁 2007
論文	A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits IFIP International Conference on Very Large Scale Integration,308-313頁 2006
論文	Design for Testability of Software-Based Self-Test for Processors 15th IEEE Asian Test Symposium,375-380頁 2006
論文	Electrical Behavior of GOS Fault affected Domino Logic Cell Third IEEE International Workshop on Electronic Design, Test & Applications,183-189頁 2006
論文	Low-Cost Hardening of Image Processing Applications Against Software Errors 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,274-279頁 2006
論文	Non-Scan Design for Single-Port-Change Delay Fault Testability IPSJ Journal 47 (6),1619-1628頁 2006
論文	Non-scan Design for Single-Port-Change Delay Fault Testability ipsjdc 2,338-347頁 2006
論文	完全故障検出効率を保証するRTLデータパスの部分強可検査性に基づくテスト容易化設計法電子情報通信学会和文論文誌D-I（ディペンダブルコンピューティング特集号） J89-D (8),1643-1653頁 2006
論文	A DFT method for RTL data paths based on partially strong testability to guarantee complete fault efficiency 14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS,306-311頁 2005
論文	Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation ETS 2005:10TH IEEE EUROPEAN TEST SYMPOSIUM, PROCEEDINGS,48-53頁 2005
論文	Design for testability based on single-port-change delay testing for data paths 14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS,254-259頁 2005
論文	Electrical analysis of a domino logic cell with GOS faults Proceedings - 2005 IEEE International Workshop on Current and Defect Based Testing, DBT 2005,31-38頁 2005
論文	縮退故障のテスト生成アルゴリズムを用いたパス遅延故障に対するテスト生成法電子情報通信学会和文論文誌D-I（LSIのテスト・検証・診断技術特集号） J88-D-I (6),1057-1064頁 2005
論文	A design scheme for delay testing of controllers using state transition information IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E87A (12),3200-3207頁 2004/12
論文	New non-scan DFT techniques to achieve 100% fault efficiency JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 20 (3),315-323頁 2004/06
論文	A design methodology to realize delay testable controllers using state transition information ETS 2004: NINTH IEEE EUROPEAN TEST SYMPOSIUM, PROCEEDINGS,168-173頁 2004
論文	Design for two-pattern testability of controller-data path circuits IEICE Transactions on Information and Systems E86-D (6),1042-1050頁 2003/06
論文	A nonscan DFT method for RTL circuits based on fixed-control testability ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE 86 (10),43-55頁 2003
論文	Reducibility of sequential test generation to combinational test generation for several delay fault models ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS,58-63頁 2003
論文	不連続再収斂順序回路の遅延故障に対するテスト生成法電子情報通信学会論文誌 Vol. J86-D-I, No. 12, pp.872-883 (12),872-883頁 2003
論文	A nonscan DFT method for controllers to provide complete fault efficiency Systems and Computers in Japan 33 (5),64-75頁 2002/05
論文	A method of test generation for path delay faults in balanced sequential circuits 20TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS,321-327頁 2002
論文	Design for two-pattern testability of controller-data path circuits PROCEEDINGS OF THE 11TH ASIAN TEST SYMPOSIUM (ATS 02) Vol. 101, No. 658, pp.61-67,73-79頁 2002
論文	レジスタ転送レベルでのデータフロー依存型回路の階層テスト容易化設計法情報処理学会論文誌 43 (5),1278-1289頁 2002
論文	A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001,331-334頁 2001
論文	Design for hierarchical two-pattern testability of data paths 10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS,11-16頁 2001
論文	Testable design of sequential circuits with improved fault efficiency VLSI DESIGN 2001: FOURTEENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN,128-133頁 2001
論文	固定制御可検査性に基づくRTL回路の非スキャンテスト容易化設計法電子情報通信学会論文誌(D1) J84-D-1 (5),454-465頁 2001
論文	A method of test generation for weakly testable data paths using test knowledge extracted from RTL description Proceedings of IEEE the 8th Asian test Symposium,5-12頁 1999
論文	New DFT techniques of non-scan sequential circuits with complete fault efficiency Proceedings Eighth Asian Test Symposium (ATS'99),263-268頁 1999
論文	A non-scan DFT method for controllers to achieve complete fault efficiency SEVENTH ASIAN TEST SYMPOSIUM (ATS'98), PROCEEDINGS,204-211頁 1998
論文	Sequential test generation based on circuit pseudo-transformation SIXTH ASIAN TEST SYMPOSIUM (ATS'97), PROCEEDINGS,62-67頁 1997
論文	回路疑似変換による順序回路テスト生成の一手法情報処理学会論文誌 38 (5),1040-1049頁 1997
論文	組合せテスト生成複雑度でテスト生成可能な順序回路構造とその応用電子情報通信学会論文誌DI J80-D-I (2),155-163頁 1997